Difference between revisions of "RealQ16s:Provisional instruction listing"
From Maths
(Created page with "This is a ''provisional'' instruction listing for the RealQ16s project. __TOC__ ==Instructions by opcode== {{RealQ16s:Provisional instruction listing/Opc...") |
m (Categorising things) |
||
| Line 12: | Line 12: | ||
[[Category:RealQ provisional instruction listings]] | [[Category:RealQ provisional instruction listings]] | ||
[[Category:RealQ16s]] | [[Category:RealQ16s]] | ||
| + | [[Category:RealQ]] | ||
Latest revision as of 23:17, 12 February 2016
This is a provisional instruction listing for the RealQ16s project.
Contents
Instructions by opcode
1 byte instructions
| Range | Operation | bits | Distinct opcodes |
Comment | Caveats | ||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0000 | 0000 | NOP
|
0000 | 0000 | x1 | Does nothing | |||||||||||||
| 0000 | 0001 | (unused) | 0000 | 0001 | (x15 opcodes) | ||||||||||||||
| ... | ... | ... | |||||||||||||||||
| 0000 | 1111 | (Unused) | 0000 | 1111 | |||||||||||||||
| 0001 | 0000 | MOV r1,r2
|
0001 | r1 | r2 | x12 | Store r1 in r2, treating them both as 16 bit registers | r1 and r2 must be different | |||||||||||
| ... | (Unused) | 0001 | 0000 | x1 | |||||||||||||||
| (Unused) | 0001 | 0101 | x1 | ||||||||||||||||
| (Unused) | 0001 | 1010 | x1 | ||||||||||||||||
| 0001 | 1111 | (Unused) | 0001 | 1111 | x1 | ||||||||||||||
| 0010 | 0000 | PUSH r1
|
0010 | 00 | r1 | x4 | Push the 16 bit register r1 | ||||||||||||
| 0010 | 0100 | POP r1
|
0010 | 01 | r1 | x4 | Pop the 16 bit register r1 | ||||||||||||
| 0010 | 1000 | MOV b1,r1L
|
0010 | 10 | r1 | x1024 (x4) | 16 bit instruction 0010 10r1 vvvv vvvv - move byte b1 given by v into low byte of register r1
|
||||||||||||
| 0010 | 1100 | MOV b1,r1H
|
0010 | 11 | r1 | x1024 (x4) | 16 bit instruction 0010 11r1 vvvv vvvv - move byte b1 given by v into high byte of register r1
|
||||||||||||
| 0011 | 0000 | MOVACO b1,r1L
|
0011 | 00 | r1 | x1024 (x4) | 16 bit instruction 0011 00r1 vvvv vvvv - move byte b1 given by v into low byte of register r1, then clear high byte of register r1.
|
||||||||||||
| 0011 | 0100 | ||||||||||||||||||
| 1111 | 1111 | (two bytes prefix) | 1111 | 1111 | x256 (x1) | 16 bit instruction 1111 1111 vvvv vvvv - rare instruction that have two bytes have this as their first byte.
|
|||||||||||||
2 byte instructions
Long instructions
RealQ16s:Provisional instruction listing/Opcode table/2 byte instructions/Long instructions
Prefixed (rare) instructions
Prefixed with 1111 1111
Every instruction in this table has 2 bytes, the first byte is 1111 1111 and the second byte is given in the table.
| Range | Operation | bits | Distinct opcodes |
Comment | Caveats | ||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0000 | 0000 | ||||||||||||||||||
| 1111 | 1111 | (four bytes prefix) | 1111 | 1111 | x256 (x1) | 16 bit instruction 1111 1111 1111 1111 vvvv vvvv - very rare instruction that have four bytes have this as their first and second bytes.
| |||||||||||||
3 byte instructions
RealQ16s:Provisional instruction listing/Opcode table/3 byte instructions
Logical instructions
These instructions are not real CPU instructions, they are allowed in assembly, and code will be generated that makes it seem as if these instructions are implemented. The listing here is alphabetical.
RealQ16s:Provisional instruction listing/Opcode table/Logical instructions
Unallocated instructions
-
MOVACO b1,r1H- Move byte b1 into high byte of register r1, then clear low byte of register r1.
Instructions by mnemonic
RealQ16s:Provisional instruction listing/Mnemonic table
