Difference between revisions of "RealQ16s:Provisional register listing"
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* '''Stride register''' | * '''Stride register''' | ||
*: {{M|1=\overbrace{\ \ \text{4 bits}\ \ \ }^\text{STRIDE} }} | *: {{M|1=\overbrace{\ \ \text{4 bits}\ \ \ }^\text{STRIDE} }} | ||
| − | + | {{:RealQ16s:Provisional register listing/Core infobox mark II}} | |
[[Category:RealQ16s]][[Category:RealQ]][[Category:RealQ provisional register listings]] | [[Category:RealQ16s]][[Category:RealQ]][[Category:RealQ provisional register listings]] | ||
Latest revision as of 14:31, 14 February 2016
These are the minimum required registers for the RealQ16s project - that is there may be more registers than this in an actual machine (depending on extensions) but these /must/ be present.
Contents
Core registers
| Core registers | |
| RealQ16s | |
| General purpose | |
|---|---|
| A (16bit) | Accumulator, ALU operand |
| B (16bit) | Base register, pointers |
| C (16bit) | Count register, offsets |
| D (16bit) | Data, communications |
| Note: | Each GP register has a L and H form, eg AL is the lower 8 bits of A |
| Programming registers | |
| IP (16bit) | Instruction pointer |
| SP (16bit) | Stack pointer |
| BP (16bit) | Stack frame pointer |
| STRIDE (4bit) | For array access |
These registers are required by all implementations of RealQ16s
- General purpose - There are 8 bytes of general purpose registers.
- There are 4 16 bit general purpose registers, A, B, C and D. Each of these is aliased to 2 8 bit registers, they are:
- AL, AH, BL, BH, CL, CH, DL and DH. That is AL is the lower byte of A and AH the upper, same for the others.
- To sum up the registers are as follows:
- [ilmath]\overbrace{\ \ \overbrace{\text{8 bits} }^\text{AL}\ \ \ \vert\ \ \ \overbrace{\text{8 bits} }^\text{AH}\ \ }^\text{A}[/ilmath] [ilmath]\Big\vert[/ilmath] [ilmath]\overbrace{\ \ \overbrace{\text{8 bits} }^\text{BL}\ \ \ \vert\ \ \ \overbrace{\text{8 bits} }^\text{BH}\ \ }^\text{B}[/ilmath] [ilmath]\Big\vert[/ilmath] [ilmath]\overbrace{\ \ \overbrace{\text{8 bits} }^\text{CL}\ \ \ \vert\ \ \ \overbrace{\text{8 bits} }^\text{CH}\ \ }^\text{C}[/ilmath] [ilmath]\Big\vert[/ilmath] [ilmath]\overbrace{\ \ \overbrace{\text{8 bits} }^\text{DL}\ \ \ \vert\ \ \ \overbrace{\text{8 bits} }^\text{DH}\ \ }^\text{D}[/ilmath]
- There are 4 16 bit general purpose registers, A, B, C and D. Each of these is aliased to 2 8 bit registers, they are:
- Instruction pointer
- [ilmath]\overbrace{\ \ \text{8 bits}\ \ \ \vert\ \ \ \text{8 bits}\ \ }^\text{IP}[/ilmath]
- Stack registers
- There are 2 stack registers, BP, which points to the base of the current stack frame and SP, which points to the head of the stack.
- [ilmath]\overbrace{\ \ \text{8 bits}\ \ \ \vert\ \ \ \text{8 bits}\ \ }^\text{BP}[/ilmath] [ilmath]\Big\vert[/ilmath] [ilmath]\overbrace{\ \ \text{8 bits}\ \ \ \vert\ \ \ \text{8 bits}\ \ }^\text{SP}[/ilmath]
- Stride register
- [ilmath]\overbrace{\ \ \text{4 bits}\ \ \ }^\text{STRIDE}[/ilmath]
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