Difference between revisions of "Notes:RealQ Architecture/1-Byte operations"
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| registers must have same size-code<ref group="N">That is must both be 16bit, low or high</ref> | | registers must have same size-code<ref group="N">That is must both be 16bit, low or high</ref> | ||
|- | |- | ||
| − | | | + | | {{C|[[Notes:RealQ instruction SWP|SWP]] r}} |
| colspan="2" | {{C|01}} | | colspan="2" | {{C|01}} | ||
| colspan="2" | {{C|11}} | | colspan="2" | {{C|11}} | ||
| − | | colspan="2" | {{C| | + | | colspan="2" | {{C|00}} |
| − | | colspan="2" | {{C| | + | | colspan="2" | {{C|rr}} |
| − | | | + | |- |
| | | | ||
| + | | colspan="2" | {{C|01}} | ||
| + | | colspan="2" | {{C|11}} | ||
| + | | colspan="2" | {{C|01}} | ||
| + | | colspan="2" | {{C|xx}} | ||
| + | | colspan="2" style="text-align:center;" | ''(see: {{C|INC}})'' | ||
|- | |- | ||
| ''(Unused)'' | | ''(Unused)'' | ||
Revision as of 20:12, 2 October 2015
| Operation | bits | Comment | Caveats | |||||||
|---|---|---|---|---|---|---|---|---|---|---|
| LOAD r1,r2 | 00 | sr2 | r1 | r2 | r1 must be 16bit, sr2=11 is unused. | |||||
| (Unused) | 00 | 11 | xx | xx | ||||||
| MOV r1,r2 | 01 | sr | r1 | r2 | registers must have same size-code[N 1] | |||||
| SWP r | 01 | 11 | 00 | rr | ||||||
| 01 | 11 | 01 | xx | (see: INC) | ||||||
| (Unused) | 01 | 11 | 1x | xx | ||||||
Opcode notes
- ↑ That is must both be 16bit, low or high
