Difference between revisions of "Notes:RealQ Architecture/1-Byte operations"

Revision as of 19:40, 2 October 2015

Operation	bits				Comment	Caveats
LOAD r1,r2	00	sr2	r1	r2	r1 must be 16bit, sr2=11 is unused.
(Unused)	00	11	xx	xx
MOV r1,r2	01	sr	r1	r2		registers must have same size-code^{[N 1]}
	01	11	xx	xx	(see: SWP)

@@ Line 8: / Line 8: @@
 | {{C|[[Notes:RealQ instruction LOAD|LOAD]] r1,r2}}
 | colspan="2" | {{C|00}}
+| colspan="2" | {{C|sr2}}
 | colspan="2" | {{C|r1}}
 | colspan="2" | {{C|r2}}
-| colspan="2" | {{C|sr2}}
 | {{C|r1}} '''must''' be 16bit, {{C|1=sr2=11}} is unused.
 |
@@ Line 16: / Line 16: @@
 | ''(Unused)''
 | colspan="2" | {{C|00}}
+| colspan="2" | {{C|11}}
 | colspan="2" | {{C|xx}}
 | colspan="2" | {{C|xx}}
-| colspan="2" | {{C|11}}
 |-
 | {{C|[[Notes:RealQ instruction MOV|MOV]] r1,r2}}
 | colspan="2" | {{C|01}}
+| colspan="2" | {{C|sr}}
 | colspan="2" | {{C|r1}}
 | colspan="2" | {{C|r2}}
-| colspan="2" | {{C|sr}}
 |
 | registers must have same size-code<ref group="N">That is must both be 16bit, low or high</ref>
@@ Line 30: / Line 30: @@
 |
 | colspan="2" | {{C|01}}
+| colspan="2" | {{C|11}}
 | colspan="2" | {{C|xx}}
 | colspan="2" | {{C|xx}}
-| colspan="2" | {{C|11}}
 | colspan="2" style="text-align:center;" | ''(see: {{C|SWP}})''
 |}