Difference between revisions of "Notes:RealQ Architecture"
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| {{C|11}} | | {{C|11}} | ||
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| − | {{ | + | |
| + | {{C|s(r)}} denotes the size of a register expression. It's identified by 2 bits: | ||
| + | |||
| + | {| class="wikitable" border="1" | ||
| + | |- | ||
| + | ! Meaning | ||
| + | ! Identifier | ||
| + | |- | ||
| + | | '''16-bit''': the operation will applied to all 16 bits of the register | ||
| + | | {{C|00}} | ||
| + | |- | ||
| + | | '''XL''': the operation will be applied to the lower 8 bits | ||
| + | | {{C|01}} | ||
| + | |- | ||
| + | | '''XH''': the operation will be applied to the higher 8 bits | ||
| + | | {{C|10}} | ||
| + | |- | ||
| + | | '''Unused''': ''' | ||
| + | | {{C|11}} | ||
| + | |} | ||
==Modes== | ==Modes== | ||
Revision as of 19:13, 2 October 2015
The RealQ architecture is a realistic architecture[Note 1] developed Quickly.
Contents
Architecture
The RealQ architecture has 4 general purpose 16 bit registers. They are A, B, C and D. Each general purpose register is further split into two smaller registers, L and H, which refer to the low byte and high byte respectively. That is XL refers to the first 8 bits (or byte) of whatever is in register X.
Conventions
We use r to denote a general purpose register. Use r1, r2,... for separating registers in an expression (example, you would write: MOV r1, r2, or just SWP r) and r may be written rr if it is neater.
A GP (general purpose) register requires 2 bits to denote, we use the following codes:
| Register | Code |
|---|---|
| A | 00 |
| B | 01 |
| C | 10 |
| D | 11 |
s(r) denotes the size of a register expression. It's identified by 2 bits:
| Meaning | Identifier |
|---|---|
| 16-bit: the operation will applied to all 16 bits of the register | 00 |
| XL: the operation will be applied to the lower 8 bits | 01 |
| XH: the operation will be applied to the higher 8 bits | 10 |
| Unused: | 11 |
Modes
The architecture defines 2 modes, Kernel and User
Operations
(Given alphabetically)
| Operation | Type | Comment |
|---|---|---|
| HLT | 3-byte | KERNEL MODE ONLY - stops the machine |
1-Byte operations
(Given alphabetically.)
| Operation | bits | Comment | Caveats | |||||||
|---|---|---|---|---|---|---|---|---|---|---|
| LOAD r1,r2 | 00 | sr2 | r1 | r2 | r1 must be 16bit, sr2=11 is unused | |||||
| (Unused) | 00 | 11 | xx | xx | ||||||
| MOV r1,r2 | 01 | sr | r1 | r2 | registers must have same size-code[N 1] | |||||
| SWP r | 01 | 11 | 00 | rr | ||||||
| INC | 01 | 11 | 01 | 00 | Only affects the A register | |||||
| INC2 | 01 | 11 | 01 | 01 | Only affects the A register | |||||
| DEC | 01 | 11 | 01 | 10 | Only affects the A register | |||||
| DEC2 | 01 | 11 | 01 | 11 | Only affects the A register | |||||
| (Unused) | 01 | 11 | 1 | x | xx | |||||
Opcode notes
- ↑ That is must both be 16bit, low or high
Notes
- ↑ In the sense of it models a real CPU that could actually exist. It deals with bytes and has no knowledge of types (in contrast to say Lua's VM)
