View source for Notes:RealQ Architecture/1-Byte operations

{| class="wikitable" border="1"
|-
! Operation
! colspan="8" | bits
! Comment
! Caveats 
|-
| {{C|[[Notes:RealQ instruction LOAD|LOAD]] r1,r2}}
| colspan="2" | {{C|00}}
| colspan="2" | {{C|sr2}}
| colspan="2" | {{C|r1}}
| colspan="2" | {{C|r2}}
| {{C|r1}} '''must''' be 16bit, {{C|1=sr2=11}} is unused.
|
|-
| ''(Unused)''
| colspan="2" | {{C|00}}
| colspan="2" | {{C|11}}
| colspan="2" | {{C|xx}}
| colspan="2" | {{C|xx}}
|-
| {{C|[[Notes:RealQ instruction MOV|MOV]] r1,r2}}
| colspan="2" | {{C|01}}
| colspan="2" | {{C|sr}}
| colspan="2" | {{C|r1}}
| colspan="2" | {{C|r2}}
|
| registers must have same size-code<ref group="N">That is must both be 16bit, low or high</ref>
|-
| {{C|[[Notes:RealQ instruction SWP|SWP]] r}}
| colspan="2" | {{C|01}}
| colspan="2" | {{C|11}}
| colspan="2" | {{C|00}}
| colspan="2" | {{C|rr}}
|-
| {{C|[[Notes:RealQ instruction INC|INC]] r}}
| colspan="2" | {{C|01}}
| colspan="2" | {{C|11}}
| colspan="2" | {{C|01}}
| colspan="2" | {{C|00}}
| Only affects the {{C|A}} register
|
|-
| {{C|[[Notes:RealQ instruction INC2|INC2]] r}}
| colspan="2" | {{C|01}}
| colspan="2" | {{C|11}}
| colspan="2" | {{C|01}}
| colspan="2" | {{C|01}}
| Only affects the {{C|A}} register
|
|-
| {{C|[[Notes:RealQ instruction DEC|DEC]] r}}
| colspan="2" | {{C|01}}
| colspan="2" | {{C|11}}
| colspan="2" | {{C|01}}
| colspan="2" | {{C|10}}
| Only affects the {{C|A}} register
|
|-
| {{C|[[Notes:RealQ instruction DEC2|DEC2]] r}}
| colspan="2" | {{C|01}}
| colspan="2" | {{C|11}}
| colspan="2" | {{C|01}}
| colspan="2" | {{C|11}}
| Only affects the {{C|A}} register
|
|-
| ''(Unused)''
| colspan="2" | {{C|01}}
| colspan="2" | {{C|11}}
| colspan="2" | {{C|1x}}
| colspan="2" | {{C|xx}}
|}


===Opcode notes===
<references group="N"/>